The invention relates to thin film transistor liquid crystal displays (TFT-LCDs), and more particularly to array substrates for use in TFT-LCDs and fabrication methods thereof.
Generally, liquid crystal displays comprise a lower substrate, an upper substrate and a liquid crystal layer interposed therebetween. The upper substrate typically comprises a color filter and a common electrode. The lower substrate typically comprises a plurality of pixel areas defined by crossing gate lines and source lines (or data lines). Each pixel area comprises a thin film transistor serving as a switching element located near the intersection of the gate and source lines and a pixel electrode electrically connected to the thin film transistor. The thin film transistor comprises a gate, a source and a drain, wherein the gate is extended from the gate line and the source is extended from the source line. The drain is electrically connected to the pixel electrode via a contact hole. The LCD further comprises a pad portion. The pad portion comprises a plurality of gate pads and a plurality of source pads (or data pads). The gate pads serve to apply signal voltages to the gate lines and the source pads serve to apply data voltages to the source lines. The gate and source pads are preferably located in a non-display area.
In order to form the array substrate, i.e., the lower substrate, processes such as deposition, photolithography, etching and stripping are repeated several times. The conventional method of forming the array substrate typically requires 4-6 masks, increasing processing errors and resulting in high production cost.
U.S. Pat. No. 6,338,989 to Ahn et al., the entirety of which is hereby incorporated by reference, discloses a 4-mask method of manufacturing an array substrate. First and second masks form a gate line, a gate pad, a data line and a data pad. A third mask forms a source, a drain and a pixel electrode and exposes a channel area. A fourth mask patterns an insulating layer to cover the gate line and the gate pad and to form a gate pad contact hole.
U.S. Pat. No. 6,567,150 to Kim, the entirety of which is hereby incorporated by reference, discloses a 6-mask method of manufacturing an array substrate, preventing defects from occurring at end portions of lines, such as pads.